1. Field of the Invention
The invention relates to an analog-to-digital converter. In particular, the invention relates to analog-to-digital conversion technologies of multistage pipelined type and cyclic type.
2. Description of the Related Art
Recently, cellular phones have incorporated a variety of additional functions such as an image capturing function, an image reproducing function, a moving image capturing function, and a moving image reproducing function. Reduced size and reduced power consumption are thus increasingly required of analog-to-digital converters (hereinafter, referred to as “AD converters”). One of the known forms of such AD converters is a cyclic AD converter which has a cyclic configuration (for example, see Japanese Patent Laid-Open Publication No. Hei 11-145830). FIG. 7 shows the configuration of a conventional cyclic AD converter. In this AD converter 150, an analog signal Vin input through a first switch 152 is sampled by a first amplifier circuit 156, and converted into a 1-bit digital value by an AD conversion circuit 158. The digital value is converted into an analog value by a DA conversion circuit 160, and subtracted from the input analog signal Vin by a subtractor circuit 162. The output of the subtractor circuit 162 is amplified by a second amplifier circuit 164, and fed back to the first amplifier circuit 156 through a second switch 154. This feedback-based cyclic processing is repeated 12 times to obtain 12 bits of digital value.
The cyclic AD converter described above is advantageous in suppressing the circuit area since it has a smaller number of elements as compared to multistage pipelined AD converters. For the reduced circuit area, however, an improvement to the conversion processing speed can sometimes be traded off. It has thus been a challenge to AD converters of cyclic type to achieve an efficient configuration that can attain both of these conflicting performances.